With rapid development of semiconductor fabrication technology, semiconductor devices are developed towards a direction of having a higher component density and a higher integration degree. As one of the most fundamental semiconductor devices, transistors have been widely used. With the improvement of the component density and the integration degree, the size of the gate electrode in planar transistors becomes smaller and smaller. However, as the feature size decreases, the ability of traditional planar transistors in controlling the channel current becomes less sufficient, which may cause short channel effect and leakage current, and thus may ultimately affect the electrical performance of the semiconductor devices.
According to existing methods, fin-field effect transistor (Fin-FET) has been proposed in order to overcome the short channel effect and suppress the leakage current. A Fin-FET may be a multi-gate device.
As an example, a Fin-FET may include a substrate, a fin structure formed on the surface of the substrate, and an isolation layer formed on the surface of the substrate. The isolation layer covers a portion of the sidewall of the fin structure and the top surface of the isolation layer is lower than the top surface of the fin structure. The Fin-FET also includes a gate structure formed across the fin structure. Specifically, the gate structure is formed on the surface of the isolation layer and the top and the side surfaces of the fin structure. The Fin-FET further includes a source region and a drain region formed in the fin structure on the two sides of the gate structure.
Moreover, the Fin-FET also includes an epitaxial layer formed in the fin structure on the two sides of the gate structure in order to improve the performance of the Fin-FET. The source region and the drain region are formed in the epitaxial layer by inducing P-type or N-type ions into the epitaxial layer. Forming the epitaxial layer may raise the surface height for the source region and the drain region so that the stress in the source region and the drain region may be released. In addition, due to the formation of the epitaxial layer, a stress may be induced to the fin structure situated under the gate structure. Therefore, the carrier mobility in the channel region may be improved.
However, with decrease in the feature size of semiconductor devices, the product yield and the reliability of existing Fin-FETs may also decrease. The disclosed fabrication method and transistor device are directed to solve one or more problems set forth above and other problems in the art.